Rajaguru, P. ORCID: 0000-0002-6041-0517, Bailey, C. ORCID: 0000-0002-9438-3879, Lu, H. ORCID: 0000-0002-4392-6562, Aliyu, A. M., Castellazzi, A., Pathirana, V., Udugampola, N., Trajkovic, T., Udrea, F., Mitcheson, P. D. and Elliott, A. D. T. (2017) Co-design/simulation of flip-chip assembly for high voltage IGBT packages. In: 23rd International workshop on Thermal Investigations of ICs and Systems (THERMINIC). THERMINIC, pp. 1-5.

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Abstract

This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical, thermal and mechniacal predictions are made in order to mitigate underfill dielectric breakdown failure and solder interconnect fatigue failure. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue.

Item Type:	Conference Proceedings
Title of Proceedings:	23rd International workshop on Thermal Investigations of ICs and Systems (THERMINIC)
Uncontrolled Keywords:	LED, UNDERFILL
Subjects:	Q Science > QA Mathematics
Faculty / School / Research Centre / Research Group:	Faculty of Engineering & Science > Centre for Numerical Modelling & Process Analysis (CNMPA) Faculty of Engineering & Science > Centre for Numerical Modelling & Process Analysis (CNMPA) > Computational Mechanics & Reliability Group (CMRG) Faculty of Engineering & Science > School of Computing & Mathematical Sciences (CMS) Faculty of Engineering & Science
Last Modified:	04 Mar 2022 13:07
URI:	http://gala.gre.ac.uk/id/eprint/8784

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