Melis, W.J.C. ORCID: 0000-0003-3779-8629 , Chizuwa, S. and Kameyama, M. (2009) Evaluation of the hierarchical temporal memory soft computing platform and its VLSI architecture. In: Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 233-238. ISBN 978-1-4244-3841-9 ISSN 0195-623X (doi:https://doi.org/10.1109/ISMVL.2009.11)

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Abstract

A large number of real world applications, like user support systems, can still not be performed easily by conventional algorithms in comparison with the human brain. Recently, such intelligence has often been reached by using probability based systems. This paper presents results on the implementation of one such user support system, namely an intention estimation information appliance system, on a Bayesian network as well as hierarchical temporal memory. The latter is a new and quite promising soft computing platform modelling the human brain, though currently only available as a software model. A second part of the paper therefore focuses on a possible VLSI architecture for hierarchical temporal memory. Since it models the human brain, communication as well as memory are of high importance for this VLSI architecture.

Item Type:	Conference Proceedings
Title of Proceedings:	Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on
Additional Information:	[1] Paper presented at the 39th International Symposium on Multiple-Valued Logic (ISMVL '09) 2009, held 21-23 May 2009, in Naha, Okinawa, Japan. [2] INSPEC Accession Number: 10690052.
Uncontrolled Keywords:	hierarchical temporal memory, VLSI, computer architecture
Subjects:	T Technology > TA Engineering (General). Civil engineering (General)
Pre-2014 Departments:	School of Engineering
Related URLs:	Publisher Organisation
Last Modified:	14 Oct 2016 09:16
URI:	http://gala.gre.ac.uk/id/eprint/6438

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