Otiaba, Kenny C. (2013) Thermal and thermo-mechanical performance of voided lead-free solder thermal interface materials for chip-scale packaged power device. PhD thesis, University of Greenwich.

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Abstract

The need to maximise thermal performance of electronic devices coupled with the continuing trends on miniaturization of electronic packages require innovative package designs for power devices and modules such as Electronic Control Unit (ECU). Chip scale packaging (CSP) technology offer promising solution for packaging power electronics. This is as a result of the technology’s relatively improved thermal performance and inherent size advantage. In CSP technology, heat removal from the device could be enhanced through the backside of the chip. Heat dissipating units such as heat spreader and/or heat sink can be attached to the backside (reverse side) of the heat generating silicon die (via TIM) in an effort to improve the surface area available for heat dissipation. TIMs are used to mechanically couple the heat generating chip to a heat sinking device and more crucially to enhance thermal transfer across the interface.

Extensive review shows that solder thermal interface materials (STIMs) apparently offer better thermal performance than comparable state-of-the-art commercial polymer-based TIMs and thus a preferable choice in packaging power devices. Nonetheless, voiding remains a major reliability concern of STIMs. This is coupled with the fact that solder joints are generally prone to fatigue failures under thermal cyclic loading. Unfortunately, the occurrence of solder voids is almost unavoidable during manufacturing process and is even predominant in lead (Pb)-free solder joints. The impacts of these voids on the thermal and mechanical performance of solder joints are not clearly understood and scarcely available in literature especially with regards to STIMs (large area solder joints).

Hence, this work aims to investigate STIM and the influence of voids on the thermo-mechanical and thermal performance of STIM. As previous results suggest that factors such as the location, configuration (spatial arrangement) and size of voids play vital roles on the exact effect of voids, extensive three dimensional (3D) finite element modelling is employed to elucidate the precise effect of these void features on a Pb-free STIM selected after thermo-mechanical fatigue test of standard Pb-free solder alloys. Finite element analysis (FEA) results show that solder voids configuration, size and location are all vital parameters in evaluating the mechanical and thermal impacts of voids. Depending on the location, configuration and size of voids; solder voids can either influence the initiation or propagation of damage in the STIM layer or the location of hot spot on the heat generating chip. Experimental techniques are further employed to compare and correlate levels of voiding and shear strength for representative Pb-free solders. Experimental results also suggest that void size, location and configuration may have an influence on the mechanical durability of solder joints.

The findings of this research work would be of interest to electronic packaging engineers especially in the automotive sector and have been disseminated through publications in peer reviewed journals and presentations in international conferences.

Item Type:	Thesis (PhD)
Additional Information:	uk.bl.ethos.601736
Uncontrolled Keywords:	solder die attach, void, chip scale package, finite element analysis, thermal resistance, thermal fatigue, lead-free solder,
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering
Pre-2014 Departments:	School of Engineering School of Engineering > Manufacturing Engineering Research Group
Last Modified:	14 Oct 2016 09:27
URI:	http://gala.gre.ac.uk/id/eprint/11391

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