Stoyanov, Stoyan ORCID: https://orcid.org/0000-0001-6091-1226, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris ORCID: https://orcid.org/0000-0002-9438-3879 (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

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Abstract

This paper discusses the Design for Reliability modelling of several System-in-Package (SiP) structures developed by NXP and advanced on the basis of Wafer Level Packaging (WLP). Two different types of Wafer Level SiP (WLSiP) are presented and discussed. The main focus is on the modelling approach that has been adopted to investigate and analyse the board level reliability of the presented SiP configurations. Thermo-mechanical non-linear Finite Element Analysis (FEA) is used to analyse the effect of various package design parameters on the reliability of the structures and to identify design trends towards package optimisation. FEA is used also to gain knowledge on moulded wafer shrinkage and related issues during the wafer level fabrication. The paper provides a brief outline and demonstration of a design methodology for reliability driven design optimisation of SiP. The study emphasises the advantages of applying the methodology to address complex design problems where several requirements may exist and uncertainties and interactions between parameters in the design are common.

Item Type:	Conference Proceedings
Title of Proceedings:	2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008
Additional Information:	[1] This paper forms part of the Proceedings of the 2nd Electronics System-Integration Technology Conference, 2008 (ESTC 2008), held 1-4 September 2008, in Greenwich, London, UK. The event was organised by the Computational Mechanics and Reliability Group of the University of Greenwich and the UK and RI Chapter of IEEE Components, Packaging and Manufacturing Technology (CPMT) Society with additional input from the IEEE and iMAPS Europe and programme sponsorship from the Innovative Electronics Manufacturing Research Centre (IeMRC). ©2008 IEEE.
Uncontrolled Keywords:	Design for Reliability modelling, System-in-Package (SiP) structures, NXP, Wafer Level Packaging (WLP), Finite Element Analysis (FEA)
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering Q Science > QA Mathematics
Pre-2014 Departments:	School of Computing & Mathematical Sciences School of Computing & Mathematical Sciences > Centre for Numerical Modelling & Process Analysis School of Computing & Mathematical Sciences > Centre for Numerical Modelling & Process Analysis > Computational Mechanics & Reliability Group School of Computing & Mathematical Sciences > Department of Computer Science School of Computing & Mathematical Sciences > Department of Computer Systems Technology School of Computing & Mathematical Sciences > Department of Mathematical Sciences
Related URLs:	Publisher Organisation Organisation
Last Modified:	13 Mar 2019 11:32
URI:	http://gala.gre.ac.uk/id/eprint/1243

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