Study of wire electrolytic-spark hybrid machining of silicon solar wafer and surface characteristics
Wang, W., Liu, Z.D., Tian, Z.J., Huang, Y.H., Liu, Z.X. and Ekere, N.N. (2008) Study of wire electrolytic-spark hybrid machining of silicon solar wafer and surface characteristics. In: 2nd Electronics System Integration Technology Conference, Greenwich, UK. IEEE Conference Publications . Institute of Electrical and Electronics Engineers, Inc, Piscataway, NJ, USA, 593-596 . ISBN 978-1-4244-2813-7 (Print), 978-1-4244-2814-4 (Electronic) (doi:10.1109/ESTC.2008.4684417)Full text not available from this repository.
In this paper, a new slicing method based on wire WESHM strategy, which combines electric discharge and anodic etching into a whole process, is presented. Experiments were conducted to evaluate effect of the machining rate, surface quality and wafer thickness of low resistance (0.1 "-J1On·cm) mono-crystalline and polycrystalline silicon on the wafer surface characteristics. The results show that with optimal electrical parameters and electrolyte, the maxim machining rate is "-J600mm2/min and wafer thickness is less than 120Jllll. In comparison to wire electrical discharge machining (WEDM), heat affected zone and harmful metal residual are remarkably diminished. Dense micron and submicron conic pores, which may be introduced by high temperature electrolytic erosion, are located in the craters and surface texture is quite even giving a dark color. The reflectance of light on the samples was measured to evaluate the effect of this texturing method. Experimental results show the reflectance on sliced wafer is even lower than the standard solar cells. Furthermore, in the case of cone-shaped pores for the formed surface, a fractal analysis was investigated to describe the extremely complicated surface structure, which was related to the reflectivity and could be useful to characterize surface topography properly. It is demonstrated that the wire electrolytic-spark hybrid machining (WESHM) technique has good potential for achieving high quality silicon wafer slices, and can provide a high efficiency, low-cost technique for the production of the low resistance silicon used in the photovoltaic industry.
|Item Type:||Conference Proceedings|
|Title of Proceedings:||2nd Electronics System Integration Technology Conference, Greenwich, UK|
|Additional Information:|| This paper was presented at the 2nd Electronics System-Integration Technology Conference 2008 (ESTC 2008. 2nd), held from 1-4 September 2008 at the University of Greenwich, UK.  This work is supported by Jiangsu Hi-Tech Program (BG2007004).  INSPEC Accession Number: 10397534.  The Proceedings were originally published in two volumes.|
|Uncontrolled Keywords:||electric resistance, etching, fault location, machining, reflectivity, silicon, surface discharges, surface resistance, surface topography, wire|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering|
|School / Department / Research Groups:||School of Engineering
Faculty of Engineering & Science > School of Engineering
|Last Modified:||21 Nov 2012 14:52|
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