Thermal effects of die-attach voids location and style on performance of chip level package
Otiaba, K.C., Bhatti, R.S., Ekere, N.N., Mallik, S., Amalu, E.H. and Ekpu, M. (2011) Thermal effects of die-attach voids location and style on performance of chip level package. In: 3rd IEEE International Conference on Adaptive Science and Technology (ICAST 2011): Proceedings. IEEE Conference Publications . Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 231-236. ISBN 9781467307581 (doi:10.1109/ICASTech.2011.6145176)Full text not available from this repository.
Thermal characterisation of chip-scale packaged power devices is crucial to the development of advanced electronic packages for communication and automotive applications. Solder thermal interface materials (STIMs) are often employed in the packaging of power semiconductors to enhance heat dissipation from the chip to the heat spreader. However, voids formation in STIMs impedes heat flow and could result in increase in the chip peak temperature. Three-dimensional finite element analysis is employed to investigate the thermal effects of lead-free solder void percentages, locations and styles on packaged semiconductor device. The thermal resistance of each voiding case is calculated to evaluate the thermal response of the electronic package. The results show that the thermal resistance and peak temperature of electronic package can significantly increase depending on the percentage, location and style of voids. The results would assist packaging and design engineers in the characterisation of the thermal impacts of different solder void patterns.
|Item Type:||Conference Proceedings|
|Title of Proceedings:||3rd IEEE International Conference on Adaptive Science and Technology (ICAST 2011): Proceedings|
|Additional Information:|| This paper was first presented at the 3rd International Conference on Adaptive Science and Technology (ICAST2011), held from 24-26 November 2011 in Abuja, Nigeria.  INSPEC Accession Number: 12526129|
|Uncontrolled Keywords:||chip-scale packaged power device, automotive applications, solder thermal interface materials (STIMs), three-dimensional finite element analysis, lead-free solder|
|Subjects:||Q Science > QA Mathematics > QA75 Electronic computers. Computer science|
Q Science > QA Mathematics > QA76 Computer software
T Technology > TK Electrical engineering. Electronics Nuclear engineering
|School / Department / Research Groups:||School of Engineering|
School of Engineering > Department of Engineering Systems
School of Engineering > Electronics Manufacturing Engineering Research Group
|Last Modified:||13 May 2013 14:02|
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