Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device
Otiaba, Kenny C., Bhatti, R.S., Ekere, N.N., Mallik, S., Alam, M.O., Amalu, E.H. and Ekpu, M. (2012) Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device. Microelectronics Reliability, 52 (7). pp. 1409-1419. ISSN 0026-2714 (doi:10.1016/j.microrel.2012.01.015)Full text not available from this repository.
Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.
|Additional Information:|| Published in Microelectronics Reliability, Volume 52, Issue 7, July 2012 - Special Section “Thermal, mechanical and multi-physics simulation and experiments in micro-electronics and micro-systems (EuroSimE 2011).”|
|Uncontrolled Keywords:||chip scale package (CSP) technology, solder thermal interface materials (STIMs), out-gassing phenomenon, defective metallisation, finite element analysis (FEA)|
|Subjects:||Q Science > Q Science (General)|
T Technology > TK Electrical engineering. Electronics Nuclear engineering
|School / Department / Research Groups:||School of Engineering|
School of Engineering > Manufacturing Engineering Research Group
|Last Modified:||08 May 2013 16:57|
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