Design for reliability for wafer level system in package
Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)Full text not available from this repository.
This paper discusses the Design for Reliability modelling of several System-in-Package (SiP) structures developed by NXP and advanced on the basis of Wafer Level Packaging (WLP). Two different types of Wafer Level SiP (WLSiP) are presented and discussed. The main focus is on the modelling approach that has been adopted to investigate and analyse the board level reliability of the presented SiP configurations. Thermo-mechanical non-linear Finite Element Analysis (FEA) is used to analyse the effect of various package design parameters on the reliability of the structures and to identify design trends towards package optimisation. FEA is used also to gain knowledge on moulded wafer shrinkage and related issues during the wafer level fabrication. The paper provides a brief outline and demonstration of a design methodology for reliability driven design optimisation of SiP. The study emphasises the advantages of applying the methodology to address complex design problems where several requirements may exist and uncertainties and interactions between parameters in the design are common.
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