computer architecture

Melis, W.J.C. ORCID: https://orcid.org/0000-0003-3779-8629, Chizuwa, S. and Kameyama, M. (2009) Evaluation of the hierarchical temporal memory soft computing platform and its VLSI architecture. In: Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 233-238. ISBN 978-1-4244-3841-9 ISSN 0195-623X (doi:10.1109/ISMVL.2009.11)

hierarchical temporal memory

Melis, W.J.C. ORCID: https://orcid.org/0000-0003-3779-8629, Chizuwa, S. and Kameyama, M. (2009) Evaluation of the hierarchical temporal memory soft computing platform and its VLSI architecture. In: Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 233-238. ISBN 978-1-4244-3841-9 ISSN 0195-623X (doi:10.1109/ISMVL.2009.11)

VLSI

Melis, W.J.C. ORCID: https://orcid.org/0000-0003-3779-8629, Chizuwa, S. and Kameyama, M. (2009) Evaluation of the hierarchical temporal memory soft computing platform and its VLSI architecture. In: Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 233-238. ISBN 978-1-4244-3841-9 ISSN 0195-623X (doi:10.1109/ISMVL.2009.11)