Design for Reliability modelling

Stoyanov, Stoyan ORCID: https://orcid.org/0000-0001-6091-1226, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris ORCID: https://orcid.org/0000-0002-9438-3879 (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

Finite Element Analysis (FEA)

Stoyanov, Stoyan ORCID: https://orcid.org/0000-0001-6091-1226, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris ORCID: https://orcid.org/0000-0002-9438-3879 (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

NXP

Stoyanov, Stoyan ORCID: https://orcid.org/0000-0001-6091-1226, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris ORCID: https://orcid.org/0000-0002-9438-3879 (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

System-in-Package (SiP) structures

Stoyanov, Stoyan ORCID: https://orcid.org/0000-0001-6091-1226, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris ORCID: https://orcid.org/0000-0002-9438-3879 (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

Wafer Level Packaging (WLP)

Stoyanov, Stoyan ORCID: https://orcid.org/0000-0001-6091-1226, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris ORCID: https://orcid.org/0000-0002-9438-3879 (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)