Skip navigation

Thermal modelling and optimisation of hot solder dip process

Thermal modelling and optimisation of hot solder dip process

Stoyanov, Stoyan ORCID: 0000-0001-6091-1226, Bailey, Christopher ORCID: 0000-0002-9438-3879, Tollafield, Peter, Crawford, Rob, Parker, Mike, Scott, Jim and Roulston, John (2012) Thermal modelling and optimisation of hot solder dip process. In: 2012 13th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2012). Institute of Electrical and Electronic Engineers, Inc., Piscataway, N.J., USA. ISBN 978-1-4673-1512-8 (doi:https://doi.org/10.1109/ESimE.2012.6191763)

Full text not available from this repository.

Abstract

The use of electronic components with coated leadfree solder terminations in high reliability and safety products and equipment has risks for their long-term reliability caused by tin-wicker growth phenomena. A potential solution to this problem is to "re-finish" the package leads by removing the tin coating from terminations and replace with conventional tin-lead solder in a post-manufacturing process known as hot solder dip (HSD).
This work presents a simulation driven approach to the characterisation of hot solder dipping, evaluation of process effect on parts' temperature gradients and heating/cooling rates, and addresses the advantages of applying an efficient model based process optimisation.
Transient thermal finite element analysis is used to evaluate the temperature distribution in a Quad Flat Package (QFP) during a double-dip hot solder dipping process developed by Micross Components Ltd. A full detailed three-dimensional model of the 208-pin 0.5 mm pitch component is developed using comprehensive characterisation of the package structure and materials based on X-Ray, SEM-EDX, cross-sectional metallurgy and 3D CT scan. Thermo-coupled measurements are compared with model temperature predictions. Model and experimental results have been used to inform the process optimisation strategy. Optimised process settings resulting in temperature ramp rates at die level within recommended manufacturer's limit are identified.

Item Type: Conference Proceedings
Title of Proceedings: 2012 13th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2012)
Additional Information: [1] This paper was presented at the 13th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, (EuroSimE 2012) held from 16-18 April 2012 in Cascais, Portugal. [2] The authors would like to acknowledge the contributions to this work made by Selex Galileo, Rolls Royce, Cassidian Electronics and General Dynamics. [3] INSPEC Accession Number: 12712088
Uncontrolled Keywords: thermal modelling, hot solder, microelectronics, analytical models, computed tomography, conductivity, heating, lead, materials, thermal analysis
Subjects: Q Science > Q Science (General)
Pre-2014 Departments: School of Computing & Mathematical Sciences
Related URLs:
Last Modified: 13 Mar 2019 11:34
Selected for GREAT 2016: None
Selected for GREAT 2017: None
Selected for GREAT 2018: None
Selected for GREAT 2019: None
URI: http://gala.gre.ac.uk/id/eprint/9445

Actions (login required)

View Item View Item