Items where Author is "Yannou, Jean-Marc"
 | Up a level |
Design for Reliability modelling
Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)
Finite Element Analysis (FEA)
Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)
NXP
Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)
System-in-Package (SiP) structures
Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)
Wafer Level Packaging (WLP)
Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)