Skip navigation

Items where Author is "Stoyanov, S."

Items where Author is "Stoyanov, S."

Up a level
Export as [feed] RSS
Group by: Item Type | Uncontrolled Keywords | No Grouping
3D printing accelerated temperature cycle Additive manufacturing adhesive bonding adhesives aerospace ball grid arrays butterfly module CFD chip scale packaging Commercial off-the shelf components composite compuational fluid dynamics (CFD) computational computational fluid dynamics computational mechanics computational modelling computer aided analysis computer modelling computer simulation conducting materials conservation curing Cutty Sark data driven prognostics delamination design design methodology Design of Experiment (DoE) method Designers electronic components electronic packages Electronic Packaging embedded die engineering computing fatigue life-time fatigue of materials FEA fine-pitch technology finite element analysis Finite Element Analysis (FEA) five process parameters flip chip flip chip devices flip-chip assembly flip-chip devices flow focused ion beam Focused Ion Beam (FIB) method gas flow Generative manufacturing historic integrated circuit interconnections integrated circuit reliability Integrated Design of Experiments (DoE) interfaces (materials) lead free solder interconnects LED displays LEDs life testing light emitting diodes manufacturing technicians material deformation Materials Materials scientist Mechanical engineering methodology micro and nano system micro-machining process microassembling microelectronic processing Modelling Monte Carlo simulation Multi-physics modeling nitrogen no-flow underfill materials Numerical Optimilation numerical optimisation numerical optimization material properties optimisation optimization organic light emitting diodes oxygen packaging particle swarm optimisation algorithm PHM pigtail fibre optic post weld stresses printing probabilities Product developers Production technicians Production technology prognostics framework prognostics health management Reduced Order Models (ROM) Refinishing Reliability reliable electronic packaging Response Surface response surface methodology scanning acoustic microscopes semiconductor device packaging semiconductor device reliability ship side-by-side dies SiP technology soldered joints solders solders thermal stress cracking stacked die structure surface mount technology Thermal Management thermal management (packaging) thermo-mechanical reliability analysis uncertainty analysis underfill warpage wave soldering X ray microscopes
Number of items: 147.

3D printing

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

accelerated temperature cycle

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

Additive manufacturing

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

adhesive bonding

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

adhesives

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

aerospace

Stoyanov, S., Mackay, W., Bailey, C., Jibb, D. and Gregson, C. (2004) Lifetime assessment of electronic components for high reliability aerospace applications. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 324-329. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396627)

ball grid arrays

Stoyanov, S., Mackay, W., Bailey, C., Jibb, D. and Gregson, C. (2004) Lifetime assessment of electronic components for high reliability aerospace applications. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 324-329. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396627)

Bailey, C., Stoyanov, S. and Lu, H. (2004) Reliability predictions for high density packaging. In: Proceeding of The Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP'04). Institute of Electrical and Electronics Engineers, Inc., Piscataway, N.J., U.S.A., pp. 121-128. ISBN 0780386205 (doi:10.1109/HPD.2004.1346684)

butterfly module

Mallik, A., Stoyanov, S., Bailey, C. and Firth, P. (2009) Design for reliability methodology for micro laser welding of pigtail fibres. In: Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4244-4161-7 (electronic), 978-1-4244-4160-0 (print) (doi:10.1109/ESIME.2009.4938409)

CFD

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2005) Optimising the wave soldering process for lead free solders. In: Proceeding of 2005 International Conference on Asian Green Electronics - Design for Manufacturability and Reliability - (2005 AGEC). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 125-128. ISBN 0780388062 (doi:10.1109/AGEC.2005.1452331)

chip scale packaging

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Commercial off-the shelf components

Stoyanov, S. and Bailey, C. (2015) Modelling the impact of refinishing processes on COTS components for use in aerospace applications. Microelectronics Reliability, 55 (9-10). pp. 1271-1279. ISSN 00262714 (doi:10.1016/j.microrel.2015.07.030)

composite

Stoyanov, S., Mason, P. and Bailey, C. (2006) Computational methodology for analysis of historic composite structures. In: Proceedings of the 5th International Conference on Engineering Computational Technology. Civil-Comp Press, Stirlingshire, UK. ISBN 1905088116 ISSN 1759-3433 (doi:10.4203/ccp.84.132)

compuational fluid dynamics (CFD)

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2004) Modelling the wave soldering process. In: Proceedings of the 6th International Conference on Electronics Materials and Packaging (EMAP 2004). Institute of Electrical and Electronics Engineers, pp. 553-558. ISBN 983251486X

computational

Stoyanov, S., Mason, P. and Bailey, C. (2006) Computational methodology for analysis of historic composite structures. In: Proceedings of the 5th International Conference on Engineering Computational Technology. Civil-Comp Press, Stirlingshire, UK. ISBN 1905088116 ISSN 1759-3433 (doi:10.4203/ccp.84.132)

computational fluid dynamics

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2005) Optimising the wave soldering process for lead free solders. In: Proceeding of 2005 International Conference on Asian Green Electronics - Design for Manufacturability and Reliability - (2005 AGEC). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 125-128. ISBN 0780388062 (doi:10.1109/AGEC.2005.1452331)

computational mechanics

Stoyanov, S., Bailey, C., Lu, H. and Cross, M. (2002) Integrated computational mechanics and optimization for design of electronic components. In: Parmee, Ian C. and Hajela, Prabhat, (eds.) Optimization In Industry. Springer Verlag, pp. 57-71. ISBN 9781852338342

Stoyanov, S., Bailey, C. and Cross, M. (2001) Integrating computational mechanics and numerical optimization for the design of material properties in electronic packages. In: Computational Modeling of Materials, Minerals and Metals Processing [Conference Proceedings]. The Mineral, Metals and Materials Society (TMS), Warrendale, PA, USA, pp. 551-562. ISBN 0873395131

computational modelling

Stoyanov, S., Bailey, C., Tang, Y.K., Marson, S., Dyer, A., Allen, D. and Desmulliez, M. (2010) Computational modelling and optimisation of the fabrication of nano-structures using focused ion beam and imprint forming technologies. Journal of Physics: Conference Series (JPCS), 253 (1):012008. ISSN 1742-6588 (Print), 1742-6596 (Online) (doi:10.1088/1742-6596/252/1/012008)

computer aided analysis

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2005) Optimising the wave soldering process for lead free solders. In: Proceeding of 2005 International Conference on Asian Green Electronics - Design for Manufacturability and Reliability - (2005 AGEC). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 125-128. ISBN 0780388062 (doi:10.1109/AGEC.2005.1452331)

computer modelling

Rosunally, Y.Z., Stoyanov, S., Bailey, C., Mason, P., Campbell, S., Monger, G. and Bell, I. (2011) Fusion approach for prognostics framework of heritage structure. IEEE Transactions on Reliability, 60 (1):570453. pp. 3-13. ISSN 0018-9529 (doi:10.1109/TR.2011.2104451)

computer simulation

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

conducting materials

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

conservation

Rosunally, Y.Z., Stoyanov, S., Bailey, C., Mason, P., Campbell, S., Monger, G. and Bell, I. (2011) Fusion approach for prognostics framework of heritage structure. IEEE Transactions on Reliability, 60 (1):570453. pp. 3-13. ISSN 0018-9529 (doi:10.1109/TR.2011.2104451)

curing

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

Cutty Sark

Rosunally, Y.Z., Stoyanov, S., Bailey, C., Mason, P., Campbell, S., Monger, G. and Bell, I. (2011) Fusion approach for prognostics framework of heritage structure. IEEE Transactions on Reliability, 60 (1):570453. pp. 3-13. ISSN 0018-9529 (doi:10.1109/TR.2011.2104451)

Stoyanov, S., Mason, P. and Bailey, C. (2006) Computational methodology for analysis of historic composite structures. In: Proceedings of the 5th International Conference on Engineering Computational Technology. Civil-Comp Press, Stirlingshire, UK. ISBN 1905088116 ISSN 1759-3433 (doi:10.4203/ccp.84.132)

data driven prognostics

Sutharssan, T., Stoyanov, S., Bailey, C. and Rosunally, Y. (2012) Data analysis techniques for real-time prognostics and health management of semiconductor devices. In: Microelectronics and Packaging. Institute of Electrical and Electronic Engineers, Inc, Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4673-0694-2 (print)

delamination

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

design

Stoyanov, S., Bailey, C., Lu, H. and Cross, M. (2002) Integrated computational mechanics and optimization for design of electronic components. In: Parmee, Ian C. and Hajela, Prabhat, (eds.) Optimization In Industry. Springer Verlag, pp. 57-71. ISBN 9781852338342

design methodology

Tang, Ying Kit, Stoyanov, S., Bailey, C. and Chan, Y.C. (2008) Uncertainty analysis to minimise risk in designing micro-electronics manufacturing processes. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 941-946. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Electronic) (doi:10.1109/ESTC.2008.4684478)

Design of Experiment (DoE) method

Tang, Ying Kit, Stoyanov, S., Bailey, C. and Chan, Y.C. (2008) Uncertainty analysis to minimise risk in designing micro-electronics manufacturing processes. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 941-946. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Electronic) (doi:10.1109/ESTC.2008.4684478)

Designers

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

electronic components

Stoyanov, S., Bailey, C., Lu, H. and Cross, M. (2002) Integrated computational mechanics and optimization for design of electronic components. In: Parmee, Ian C. and Hajela, Prabhat, (eds.) Optimization In Industry. Springer Verlag, pp. 57-71. ISBN 9781852338342

electronic packages

Stoyanov, S., Bailey, C. and Cross, M. (2001) Integrating computational mechanics and numerical optimization for the design of material properties in electronic packages. In: Computational Modeling of Materials, Minerals and Metals Processing [Conference Proceedings]. The Mineral, Metals and Materials Society (TMS), Warrendale, PA, USA, pp. 551-562. ISBN 0873395131

Electronic Packaging

Stoyanov, S. and Bailey, C. (2002) Response Surface Modeling and Optimisation for Reliable Electronic Products. In: The Fifth International IEEE Symposium on High Density Packaging and Component Failure Analysis in Electronics Manufacturing. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 49-57. ISBN 0780398238

embedded die

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

engineering computing

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2005) Optimising the wave soldering process for lead free solders. In: Proceeding of 2005 International Conference on Asian Green Electronics - Design for Manufacturability and Reliability - (2005 AGEC). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 125-128. ISBN 0780388062 (doi:10.1109/AGEC.2005.1452331)

fatigue life-time

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

fatigue of materials

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

FEA

Stoyanov, S., Mason, P. and Bailey, C. (2006) Computational methodology for analysis of historic composite structures. In: Proceedings of the 5th International Conference on Engineering Computational Technology. Civil-Comp Press, Stirlingshire, UK. ISBN 1905088116 ISSN 1759-3433 (doi:10.4203/ccp.84.132)

fine-pitch technology

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

finite element analysis

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

Stoyanov, S., Mason, P. and Bailey, C. (2006) Computational methodology for analysis of historic composite structures. In: Proceedings of the 5th International Conference on Engineering Computational Technology. Civil-Comp Press, Stirlingshire, UK. ISBN 1905088116 ISSN 1759-3433 (doi:10.4203/ccp.84.132)

Stoyanov, S., Mackay, W., Bailey, C., Jibb, D. and Gregson, C. (2004) Lifetime assessment of electronic components for high reliability aerospace applications. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 324-329. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396627)

Stoyanov, S. and Bailey, C. (2003) Optimization and finite element analysis for reliable electronic packaging. In: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-electronics and Micro-systems. Proceedings of EuroSimE 2003. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 391-399. ISBN 0780370546

Finite Element Analysis (FEA)

Mallik, A., Stoyanov, S., Bailey, C. and Firth, P. (2009) Design for reliability methodology for micro laser welding of pigtail fibres. In: Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4244-4161-7 (electronic), 978-1-4244-4160-0 (print) (doi:10.1109/ESIME.2009.4938409)

five process parameters

Mallik, A., Stoyanov, S., Bailey, C. and Firth, P. (2009) Design for reliability methodology for micro laser welding of pigtail fibres. In: Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4244-4161-7 (electronic), 978-1-4244-4160-0 (print) (doi:10.1109/ESIME.2009.4938409)

flip chip

Stoyanov, S., Bailey, C. and Cross, M. (2002) Optimisation modelling for flip-chip solder joint reliability. Soldering and Surface Mount Technology, 14 (1). pp. 49-58. ISSN 0954-0911 (doi:10.1108/09540910210416477)

flip chip devices

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

flip-chip assembly

Lu, H., Stoyanov, S., Bailey, C., Hung, K.C. and Chan, Y.C. (2001) A modelling and experimental analysis of the no-flow underfill process for flip-chip assembly. In: Proceedings of the 4th International Symposium on Electronic Packaging Technology. Institute of Electrical and Electronics Engineers, Inc., pp. 338-343. ISBN 0780398114

flip-chip devices

Bailey, C., Stoyanov, S. and Lu, H. (2004) Reliability predictions for high density packaging. In: Proceeding of The Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP'04). Institute of Electrical and Electronics Engineers, Inc., Piscataway, N.J., U.S.A., pp. 121-128. ISBN 0780386205 (doi:10.1109/HPD.2004.1346684)

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

flow

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2005) Optimising the wave soldering process for lead free solders. In: Proceeding of 2005 International Conference on Asian Green Electronics - Design for Manufacturability and Reliability - (2005 AGEC). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 125-128. ISBN 0780388062 (doi:10.1109/AGEC.2005.1452331)

focused ion beam

Tang, Y.K., Stoyanov, S., Bailey, C. and Chan, Y.C. (2008) Optimisation methodology for risk mitigation in advanced micro-system electronics manufacturing. In: EngOpt 2008 - International Conference on Engineering Optimization. Universidade Federal do Rio de Janeiro, Rio de Janeiro, Brazil. ISBN 978-85-7650-152-7

Focused Ion Beam (FIB) method

Tang, Ying Kit, Stoyanov, S., Bailey, C. and Chan, Y.C. (2008) Uncertainty analysis to minimise risk in designing micro-electronics manufacturing processes. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 941-946. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Electronic) (doi:10.1109/ESTC.2008.4684478)

gas flow

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2004) Modelling the wave soldering process. In: Proceedings of the 6th International Conference on Electronics Materials and Packaging (EMAP 2004). Institute of Electrical and Electronics Engineers, pp. 553-558. ISBN 983251486X

Generative manufacturing

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

historic

Stoyanov, S., Mason, P. and Bailey, C. (2006) Computational methodology for analysis of historic composite structures. In: Proceedings of the 5th International Conference on Engineering Computational Technology. Civil-Comp Press, Stirlingshire, UK. ISBN 1905088116 ISSN 1759-3433 (doi:10.4203/ccp.84.132)

integrated circuit interconnections

Stoyanov, S., Mackay, W., Bailey, C., Jibb, D. and Gregson, C. (2004) Lifetime assessment of electronic components for high reliability aerospace applications. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 324-329. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396627)

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

integrated circuit reliability

Stoyanov, S., Mackay, W., Bailey, C., Jibb, D. and Gregson, C. (2004) Lifetime assessment of electronic components for high reliability aerospace applications. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 324-329. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396627)

Integrated Design of Experiments (DoE)

Mallik, A., Stoyanov, S., Bailey, C. and Firth, P. (2009) Design for reliability methodology for micro laser welding of pigtail fibres. In: Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4244-4161-7 (electronic), 978-1-4244-4160-0 (print) (doi:10.1109/ESIME.2009.4938409)

interfaces (materials)

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

lead free solder interconnects

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

LED displays

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

LEDs

Sutharssan, T., Stoyanov, S., Bailey, C. and Rosunally, Y. (2012) Data analysis techniques for real-time prognostics and health management of semiconductor devices. In: Microelectronics and Packaging. Institute of Electrical and Electronic Engineers, Inc, Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4673-0694-2 (print)

life testing

Stoyanov, S., Mackay, W., Bailey, C., Jibb, D. and Gregson, C. (2004) Lifetime assessment of electronic components for high reliability aerospace applications. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 324-329. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396627)

light emitting diodes

Sutharssan, T., Stoyanov, S., Bailey, C. and Rosunally, Y. (2012) Data analysis techniques for real-time prognostics and health management of semiconductor devices. In: Microelectronics and Packaging. Institute of Electrical and Electronic Engineers, Inc, Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4673-0694-2 (print)

manufacturing technicians

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

material deformation

Stoyanov, S., Bailey, C., Tang, Y.K., Marson, S., Dyer, A., Allen, D. and Desmulliez, M. (2010) Computational modelling and optimisation of the fabrication of nano-structures using focused ion beam and imprint forming technologies. Journal of Physics: Conference Series (JPCS), 253 (1):012008. ISSN 1742-6588 (Print), 1742-6596 (Online) (doi:10.1088/1742-6596/252/1/012008)

Materials

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

Materials scientist

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

Mechanical engineering

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

methodology

Tang, Y.K., Stoyanov, S., Bailey, C. and Chan, Y.C. (2008) Optimisation methodology for risk mitigation in advanced micro-system electronics manufacturing. In: EngOpt 2008 - International Conference on Engineering Optimization. Universidade Federal do Rio de Janeiro, Rio de Janeiro, Brazil. ISBN 978-85-7650-152-7

micro and nano system

Tang, Y.K., Stoyanov, S., Bailey, C. and Chan, Y.C. (2008) Optimisation methodology for risk mitigation in advanced micro-system electronics manufacturing. In: EngOpt 2008 - International Conference on Engineering Optimization. Universidade Federal do Rio de Janeiro, Rio de Janeiro, Brazil. ISBN 978-85-7650-152-7

micro-machining process

Tang, Ying Kit, Stoyanov, S., Bailey, C. and Chan, Y.C. (2008) Uncertainty analysis to minimise risk in designing micro-electronics manufacturing processes. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 941-946. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Electronic) (doi:10.1109/ESTC.2008.4684478)

microassembling

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

microelectronic processing

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

Modelling

Stoyanov, S. and Bailey, C. (2015) Modelling the impact of refinishing processes on COTS components for use in aerospace applications. Microelectronics Reliability, 55 (9-10). pp. 1271-1279. ISSN 00262714 (doi:10.1016/j.microrel.2015.07.030)

Stoyanov, S., Mason, P. and Bailey, C. (2006) Computational methodology for analysis of historic composite structures. In: Proceedings of the 5th International Conference on Engineering Computational Technology. Civil-Comp Press, Stirlingshire, UK. ISBN 1905088116 ISSN 1759-3433 (doi:10.4203/ccp.84.132)

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2004) Modelling the wave soldering process. In: Proceedings of the 6th International Conference on Electronics Materials and Packaging (EMAP 2004). Institute of Electrical and Electronics Engineers, pp. 553-558. ISBN 983251486X

Monte Carlo simulation

Mallik, A., Stoyanov, S., Bailey, C. and Firth, P. (2009) Design for reliability methodology for micro laser welding of pigtail fibres. In: Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4244-4161-7 (electronic), 978-1-4244-4160-0 (print) (doi:10.1109/ESIME.2009.4938409)

Multi-physics modeling

Stoyanov, S. and Bailey, C. (2002) Response Surface Modeling and Optimisation for Reliable Electronic Products. In: The Fifth International IEEE Symposium on High Density Packaging and Component Failure Analysis in Electronics Manufacturing. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 49-57. ISBN 0780398238

nitrogen

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2005) Optimising the wave soldering process for lead free solders. In: Proceeding of 2005 International Conference on Asian Green Electronics - Design for Manufacturability and Reliability - (2005 AGEC). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 125-128. ISBN 0780388062 (doi:10.1109/AGEC.2005.1452331)

no-flow underfill materials

Lu, H., Stoyanov, S., Bailey, C., Hung, K.C. and Chan, Y.C. (2001) A modelling and experimental analysis of the no-flow underfill process for flip-chip assembly. In: Proceedings of the 4th International Symposium on Electronic Packaging Technology. Institute of Electrical and Electronics Engineers, Inc., pp. 338-343. ISBN 0780398114

Numerical Optimilation

Stoyanov, S. and Bailey, C. (2002) Response Surface Modeling and Optimisation for Reliable Electronic Products. In: The Fifth International IEEE Symposium on High Density Packaging and Component Failure Analysis in Electronics Manufacturing. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 49-57. ISBN 0780398238

numerical optimisation

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

numerical optimization material properties

Stoyanov, S., Bailey, C. and Cross, M. (2001) Integrating computational mechanics and numerical optimization for the design of material properties in electronic packages. In: Computational Modeling of Materials, Minerals and Metals Processing [Conference Proceedings]. The Mineral, Metals and Materials Society (TMS), Warrendale, PA, USA, pp. 551-562. ISBN 0873395131

optimisation

Tang, Y.K., Stoyanov, S., Bailey, C. and Chan, Y.C. (2008) Optimisation methodology for risk mitigation in advanced micro-system electronics manufacturing. In: EngOpt 2008 - International Conference on Engineering Optimization. Universidade Federal do Rio de Janeiro, Rio de Janeiro, Brazil. ISBN 978-85-7650-152-7

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2005) Optimising the wave soldering process for lead free solders. In: Proceeding of 2005 International Conference on Asian Green Electronics - Design for Manufacturability and Reliability - (2005 AGEC). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 125-128. ISBN 0780388062 (doi:10.1109/AGEC.2005.1452331)

optimization

Stoyanov, S., Bailey, C. and Cross, M. (2002) Optimisation modelling for flip-chip solder joint reliability. Soldering and Surface Mount Technology, 14 (1). pp. 49-58. ISSN 0954-0911 (doi:10.1108/09540910210416477)

organic light emitting diodes

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

oxygen

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2005) Optimising the wave soldering process for lead free solders. In: Proceeding of 2005 International Conference on Asian Green Electronics - Design for Manufacturability and Reliability - (2005 AGEC). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 125-128. ISBN 0780388062 (doi:10.1109/AGEC.2005.1452331)

packaging

Bailey, C., Stoyanov, S. and Lu, H. (2004) Reliability predictions for high density packaging. In: Proceeding of The Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP'04). Institute of Electrical and Electronics Engineers, Inc., Piscataway, N.J., U.S.A., pp. 121-128. ISBN 0780386205 (doi:10.1109/HPD.2004.1346684)

particle swarm optimisation algorithm

Mallik, A., Stoyanov, S., Bailey, C. and Firth, P. (2009) Design for reliability methodology for micro laser welding of pigtail fibres. In: Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4244-4161-7 (electronic), 978-1-4244-4160-0 (print) (doi:10.1109/ESIME.2009.4938409)

PHM

Sutharssan, T., Stoyanov, S., Bailey, C. and Rosunally, Y. (2012) Data analysis techniques for real-time prognostics and health management of semiconductor devices. In: Microelectronics and Packaging. Institute of Electrical and Electronic Engineers, Inc, Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4673-0694-2 (print)

pigtail fibre optic

Mallik, A., Stoyanov, S., Bailey, C. and Firth, P. (2009) Design for reliability methodology for micro laser welding of pigtail fibres. In: Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4244-4161-7 (electronic), 978-1-4244-4160-0 (print) (doi:10.1109/ESIME.2009.4938409)

post weld stresses

Mallik, A., Stoyanov, S., Bailey, C. and Firth, P. (2009) Design for reliability methodology for micro laser welding of pigtail fibres. In: Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4244-4161-7 (electronic), 978-1-4244-4160-0 (print) (doi:10.1109/ESIME.2009.4938409)

printing

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

probabilities

Rosunally, Y.Z., Stoyanov, S., Bailey, C., Mason, P., Campbell, S., Monger, G. and Bell, I. (2011) Fusion approach for prognostics framework of heritage structure. IEEE Transactions on Reliability, 60 (1):570453. pp. 3-13. ISSN 0018-9529 (doi:10.1109/TR.2011.2104451)

Product developers

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

Production technicians

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

Production technology

Bailey, C., Stoyanov, S., Tilford, T. and Tourloukis, G. (2016) Modelling methodologies for quality assessment of 3D inkjet printed electronic products. In: 3rd Fraunhofer Direct Digital Manufacturing Conference, DDMC 2016. Proceedings. Fraunhofer Verlag, Stuttgart. ISBN 978-3-8396-9128-1 ISSN 978-3-8396-1001-5 (Online)

prognostics framework

Rosunally, Y.Z., Stoyanov, S., Bailey, C., Mason, P., Campbell, S., Monger, G. and Bell, I. (2011) Fusion approach for prognostics framework of heritage structure. IEEE Transactions on Reliability, 60 (1):570453. pp. 3-13. ISSN 0018-9529 (doi:10.1109/TR.2011.2104451)

prognostics health management

Sutharssan, T., Stoyanov, S., Bailey, C. and Rosunally, Y. (2012) Data analysis techniques for real-time prognostics and health management of semiconductor devices. In: Microelectronics and Packaging. Institute of Electrical and Electronic Engineers, Inc, Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4673-0694-2 (print)

Reduced Order Models (ROM)

Tang, Ying Kit, Stoyanov, S., Bailey, C. and Chan, Y.C. (2008) Uncertainty analysis to minimise risk in designing micro-electronics manufacturing processes. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 941-946. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Electronic) (doi:10.1109/ESTC.2008.4684478)

Refinishing

Stoyanov, S. and Bailey, C. (2015) Modelling the impact of refinishing processes on COTS components for use in aerospace applications. Microelectronics Reliability, 55 (9-10). pp. 1271-1279. ISSN 00262714 (doi:10.1016/j.microrel.2015.07.030)

Reliability

Stoyanov, S. and Bailey, C. (2015) Modelling the impact of refinishing processes on COTS components for use in aerospace applications. Microelectronics Reliability, 55 (9-10). pp. 1271-1279. ISSN 00262714 (doi:10.1016/j.microrel.2015.07.030)

Stoyanov, S., Bailey, C. and Cross, M. (2002) Optimisation modelling for flip-chip solder joint reliability. Soldering and Surface Mount Technology, 14 (1). pp. 49-58. ISSN 0954-0911 (doi:10.1108/09540910210416477)

Stoyanov, S. and Bailey, C. (2002) Response Surface Modeling and Optimisation for Reliable Electronic Products. In: The Fifth International IEEE Symposium on High Density Packaging and Component Failure Analysis in Electronics Manufacturing. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 49-57. ISBN 0780398238

reliable electronic packaging

Stoyanov, S. and Bailey, C. (2003) Optimization and finite element analysis for reliable electronic packaging. In: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-electronics and Micro-systems. Proceedings of EuroSimE 2003. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 391-399. ISBN 0780370546

Response Surface

Stoyanov, S. and Bailey, C. (2002) Response Surface Modeling and Optimisation for Reliable Electronic Products. In: The Fifth International IEEE Symposium on High Density Packaging and Component Failure Analysis in Electronics Manufacturing. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 49-57. ISBN 0780398238

response surface methodology

Mallik, A., Stoyanov, S., Bailey, C. and Firth, P. (2009) Design for reliability methodology for micro laser welding of pigtail fibres. In: Thermal, Mechanical and Multi-Physics simulation and Experiments in Microelectronics and Microsystems. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 1-7. ISBN 978-1-4244-4161-7 (electronic), 978-1-4244-4160-0 (print) (doi:10.1109/ESIME.2009.4938409)

scanning acoustic microscopes

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

semiconductor device packaging

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

semiconductor device reliability

Bailey, C., Stoyanov, S. and Lu, H. (2004) Reliability predictions for high density packaging. In: Proceeding of The Sixth IEEE CPMT Conference on High Density Microsystem Design and Packaging and Component Failure Analysis (HDP'04). Institute of Electrical and Electronics Engineers, Inc., Piscataway, N.J., U.S.A., pp. 121-128. ISBN 0780386205 (doi:10.1109/HPD.2004.1346684)

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

ship

Stoyanov, S., Mason, P. and Bailey, C. (2006) Computational methodology for analysis of historic composite structures. In: Proceedings of the 5th International Conference on Engineering Computational Technology. Civil-Comp Press, Stirlingshire, UK. ISBN 1905088116 ISSN 1759-3433 (doi:10.4203/ccp.84.132)

side-by-side dies

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

SiP technology

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

soldered joints

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

solders

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

Desmulliez, M.P.Y., Kay, R.W., Stoyanov, S. and Bailey, C. (2004) Stencil printing at sub-100 microns pitch. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 354-358. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396633)

solders thermal stress cracking

Stoyanov, S., Mackay, W., Bailey, C., Jibb, D. and Gregson, C. (2004) Lifetime assessment of electronic components for high reliability aerospace applications. In: Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 324-329. ISBN 0780388216 (doi:10.1109/EPTC.2004.1396627)

stacked die

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

structure

Stoyanov, S., Mason, P. and Bailey, C. (2006) Computational methodology for analysis of historic composite structures. In: Proceedings of the 5th International Conference on Engineering Computational Technology. Civil-Comp Press, Stirlingshire, UK. ISBN 1905088116 ISSN 1759-3433 (doi:10.4203/ccp.84.132)

surface mount technology

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

Thermal Management

Stoyanov, S. and Bailey, C. (2002) Response Surface Modeling and Optimisation for Reliable Electronic Products. In: The Fifth International IEEE Symposium on High Density Packaging and Component Failure Analysis in Electronics Manufacturing. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 49-57. ISBN 0780398238

thermal management (packaging)

Stoyanov, S., Kay, R., Bailey, C., Desmuilliez, M. and Hendriksen, M. (2003) Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives. In: Proceedings of 5th Electronics Packaging Technology Conference (EPTC 2003). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 797-802. ISBN 0780382056 (doi:10.1109/EPTC.2003.1271627)

thermo-mechanical reliability analysis

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

uncertainty analysis

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

underfill

Stoyanov, S., Bailey, C. and Cross, M. (2002) Optimisation modelling for flip-chip solder joint reliability. Soldering and Surface Mount Technology, 14 (1). pp. 49-58. ISSN 0954-0911 (doi:10.1108/09540910210416477)

warpage

Bailey, C., Stoyanov, S., Strusevich, N. and Yannou, J.-M. (2007) Reliability analysis of SiP structures. HDP'07: Proceedings of the 2007 International Symposium on High Density Packaging and Microsystem Integration. Institute of Electrical and Electronics Engineers, Inc., New York, p. 38. ISBN 9781424412525 (doi:10.1109/HDP.2007.4283556)

wave soldering

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2005) Optimising the wave soldering process for lead free solders. In: Proceeding of 2005 International Conference on Asian Green Electronics - Design for Manufacturability and Reliability - (2005 AGEC). Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 125-128. ISBN 0780388062 (doi:10.1109/AGEC.2005.1452331)

Stoyanov, S., Bailey, C., Saxena, N. and Adams, S. (2004) Modelling the wave soldering process. In: Proceedings of the 6th International Conference on Electronics Materials and Packaging (EMAP 2004). Institute of Electrical and Electronics Engineers, pp. 553-558. ISBN 983251486X

X ray microscopes

Lu, H., Hung, K.C., Stoyanov, S., Bailey, C. and Chan, Y.C. (2002) No-flow underfill flip chip assembly–an experimental and modeling analysis. Microelectronics Reliability, 42 (8). pp. 1205-1212. ISSN 0026-2714 (doi:10.1016/S0026-2714(02)00092-6)

This list was generated on Thu Apr 26 04:49:38 2018 BST.