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Items where Author is "Rizvi, Jahir"

Items where Author is "Rizvi, Jahir"

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Number of items: 5.

Design for Reliability modelling

Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

Finite Element Analysis (FEA)

Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

NXP

Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

System-in-Package (SiP) structures

Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

Wafer Level Packaging (WLP)

Stoyanov, Stoyan, Strusevitch, Nadia, Rizvi, Jahir, Georgel, Vincent, Yannou, Jean-Marc and Bailey, Chris (2008) Design for reliability for wafer level system in package. In: 2nd Electronics System-Integration Technology Conference, 2008. ESTC 2008. Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, USA, pp. 293-298. ISBN 978-1-4244-2814-4 (Print), 978-1-4244-2813-7 (Online) (doi:10.1109/ESTC.2008.4684364)

This list was generated on Wed Jun 20 08:46:29 2018 BST.