Items where Author is "Chizuwa, S."
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cellular phone intention estimation
Melis, W.J.C., Chizuwa, S. and Kameyama, M. (2010) Evaluation of herarchical temporal memory for a real world application. In: Innovative Computing, Information and Control (ICICIC), 2009 Fourth International Conference on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 144-147. ISBN 978-1-4244-5543-0 (doi:10.1109/ICICIC.2009.195)
computer architecture
Melis, W.J.C., Chizuwa, S. and Kameyama, M. (2009) Evaluation of the hierarchical temporal memory soft computing platform and its VLSI architecture. In: Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 233-238. ISBN 978-1-4244-3841-9 ISSN 0195-623X (doi:10.1109/ISMVL.2009.11)
hierarchical temporal memory
Melis, W.J.C., Chizuwa, S. and Kameyama, M. (2010) Evaluation of herarchical temporal memory for a real world application. In: Innovative Computing, Information and Control (ICICIC), 2009 Fourth International Conference on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 144-147. ISBN 978-1-4244-5543-0 (doi:10.1109/ICICIC.2009.195)
Melis, W.J.C., Chizuwa, S. and Kameyama, M. (2009) Evaluation of the hierarchical temporal memory soft computing platform and its VLSI architecture. In: Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 233-238. ISBN 978-1-4244-3841-9 ISSN 0195-623X (doi:10.1109/ISMVL.2009.11)
real world application
Melis, W.J.C., Chizuwa, S. and Kameyama, M. (2010) Evaluation of herarchical temporal memory for a real world application. In: Innovative Computing, Information and Control (ICICIC), 2009 Fourth International Conference on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 144-147. ISBN 978-1-4244-5543-0 (doi:10.1109/ICICIC.2009.195)
VLSI
Melis, W.J.C., Chizuwa, S. and Kameyama, M. (2009) Evaluation of the hierarchical temporal memory soft computing platform and its VLSI architecture. In: Multiple-Valued Logic, 2009. ISMVL '09. 39th International Symposium on. Institute of Electrical and Electronics Engineers, Piscataway, NJ, USA, pp. 233-238. ISBN 978-1-4244-3841-9 ISSN 0195-623X (doi:10.1109/ISMVL.2009.11)