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Performance evaluation of the register insertion protocol for voice-data integration

Performance evaluation of the register insertion protocol for voice-data integration

Mckenzie, S. (1997) Performance evaluation of the register insertion protocol for voice-data integration. Computer Communications, 20 (9). pp. 789-797. ISSN 0140-3664 (doi:10.1016/S0140-3664(97)00076-5)

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Abstract

The performance of the register insertion protocol for mixed voice-data traffic is investigated by simulation. The simulation model incorporates a common insertion buffer for station and ring packets. Bandwidth allocation is achieved by imposing a queue limit at each node. A simple priority scheme is introduced by allowing the queue limit to vary from node to node. This enables voice traffic to be given priority over data. The effect on performance of various operational and design parameters such as ratio of voice to data traffic, queue limit and voice packet size is investigated. Comparisons are made where possible with related work on other protocols proposed for voice-data integration. The main conclusions are: (a) there is a general degradation of performance as the ratio of voice traffic to data traffic increases, (b) substantial improvement in performance can be achieved by restricting the queue length at data nodes and (c) for a given ring utilisation, smaller voice packets result in lower delays for both voice and data traffic.

Item Type: Article
Uncontrolled Keywords: register insertion, voice-data integration, simulation
Subjects: Q Science > QA Mathematics
Pre-2014 Departments: School of Computing & Mathematical Sciences
School of Computing & Mathematical Sciences > Computer & Computational Science Research Group
School of Computing & Mathematical Sciences > Department of Computer Systems Technology
Related URLs:
Last Modified: 14 Oct 2016 08:59
Selected for GREAT 2016: None
Selected for GREAT 2017: None
Selected for GREAT 2018: None
URI: http://gala.gre.ac.uk/id/eprint/91

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