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Performance analysis of a register insertion ring with a variable size buffer

Performance analysis of a register insertion ring with a variable size buffer

McKenzie, S. (1997) Performance analysis of a register insertion ring with a variable size buffer. Applied Mathematical Modelling, 21 (5). pp. 293-299. ISSN 0307-904X (doi:10.1016/S0307-904X(97)00029-2)

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Abstract

There has been a recent revival of interest in the register insertion (RI) protocol because of its high throughput and low delay characteristics. Several variants of the protocol have been investigated with a view to integrating voice and data applications on a single local area network (LAN). In this paper the performance of an RI ring with a variable size buffer is studied by modelling and simulation. The chief advantage of the proposed scheme is that an efficient but simple bandwidth allocation scheme is easily incorporated. Approximate formulas are derived for queue lengths, queueing times, and total end-to-end transfer delays. The results are compared with previous analyses and with simulation estimates. The effectiveness of the proposed protocol in ensuring fairness of access under conditions of heavy and unequal loading is investigated.

Item Type: Article
Uncontrolled Keywords: register insertion, starvation, performance, simulation
Subjects: Q Science > QA Mathematics
Pre-2014 Departments: School of Computing & Mathematical Sciences
School of Computing & Mathematical Sciences > Computer & Computational Science Research Group
School of Computing & Mathematical Sciences > Department of Computer Systems Technology
Related URLs:
Last Modified: 14 Oct 2016 08:59
Selected for GREAT 2016: None
Selected for GREAT 2017: None
Selected for GREAT 2018: None
URI: http://gala.gre.ac.uk/id/eprint/90

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